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LTC4215 Hot Swap Controller with I2C Compatible Monitoring FEATURES

DESCRIPTIO
Allows Safe Insertion into Live Backplane 8-Bit ADC Monitors Current and Voltage I2C/SMBus Interface Wide Operating Voltage Range: 2.9V to 15V dI/dt Controlled Soft-Start High Side Drive for External N-Channel MOSFET No External Gate Capacitor Required Input Overvoltage/Undervoltage Protection Optional Latchoff or Auto-Retry After Faults Alerts Host After Faults Inrush Current Limit with Foldback Available in 24-Lead (4mm x 5mm) QFN and 16-Lead Narrow SSOP Packages
The LTC(R)4215 Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, board supply voltage and inrush current are ramped up at an adjustable rate. An I2C interface and onboard ADC allow for monitoring of load current, voltage and fault status. The device features adjustable foldback current limit and a soft-start pin that sets the dI/dt of the inrush current. An I2C interface may configure the part to latch off or automatically restart after the LTC4215 detects a current limit fault. The controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card, and power-up either automatically upon insertion or wait for an I2C command to turn on.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Live Board Insertion Electronic Circuit Breakers Computers, Servers Platform Management
TYPICAL APPLICATIO
12V 34k
0.005
FDC653N
+
CL 10 1.74k 20V 2.67k UV VDD SENSE+ SENSE- GATE SOURCE OV FB SDAO EN SDAI LTC4215UFD SCL ADIN ALERT GPIO INTVCC ON TIMER SS GND 68nF 0.1F CONNECTOR 2 CONNECTOR 1
VOUT 12V 30.1k VDD 10V/DIV INRUSH CURRENT 2.5A/DIV CONTACT BOUNCE
3.57k
SDA SCL ALERT 0.1F
24k
VOUT 10V/DIV VGPIO (POWERGOOD) 10V/DIV
4215 TA01a
CL = 12000F GND BACKPLANE PLUG-IN CARD
U
50ms/DIV
4215 TA01b
U
U
4215fb
1
LTC4215 ABSOLUTE AXI U RATI GS
Supply Voltage (VDD) ................................ -0.3V to 24V Supply Voltage (INTVCC) .......................... -0.3V to 6.5V Input Voltages GATE-SOURCE (Note 3) .......................... -0.3V to 5V SENSE+, SENSE- ................ VDD - 0.3V to VDD + 0.3V SOURCE.................................................... -5V to 24V EN, FB, ON, OV, UV ................................ -0.3V to 12V ADR0, ADR1, ADR2, TIMER, ADIN, SS................................ -0.3V to INTVCC + 0.3V ALERT SCL, SDA, SDAI, SDAO ............ -0.3V to 6.5V
PACKAGE/ORDER I FOR ATIO
TOP VIEW SENSE- VDD UV SS GND ON SDA SCL 1 2 3 4 5 6 7 8 16 GATE 15 SOURCE 14 FB 13 GPIO 12 INTVCC 11 TIMER 10 ADR0 9 ALERT
24 23 22 21 20 UV 1 OV 2 SS 3 GND 4 ON 5 EN 6 SDAO 7 8 SDAI 9 10 11 12 ALERT SCL NC ADR0 25 19 FB 18 GPIO 17 INTVCC 16 TIMER 15 ADIN 14 ADR2 13 ADR1
GN PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 130C/W
UFD PACKAGE 24-LEAD (4mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 25) NOT GUARANTEED LOW IMPEDANCE TO GND, ELECTRICAL CONNECTION OPTIONAL
ORDER PART NUMBER LTC4215CGN LTC4215IGN
GN PART MARKING 4215 4215I
ORDER PART NUMBER LTC4215CUFD LTC4215IUFD
UFD PART MARKING* 4215 4215
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
SOURCE
SENSE+
SENSE-
GATE
VDD
2
U
U
W
WW U
W
(Notes 1, 2)
Output Voltages GATE, GPIO............................................ -0.3V to 24V Operating Temperature Range LTC4215C ................................................ 0C to 70C LTC4215I ............................................. -40C to 85C Storage Temperature Range SSOP ................................................. -65C to 150C QFN.................................................... -65C to 125C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300C
TOP VIEW
4215fb
LTC4215
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 12V unless otherwise noted.
SYMBOL Supplies VDD VOV(VDD) IDD VDD(UVL) VDD(HYST) INTVCC INTVCC(UVL) INTVCC(HYST) VSENSE(TH) VSENSE Input Supply Range Input Supply Overvoltage Threshold Input Supply Current Input Supply Undervoltage Lockout Input Supply Undervoltage Lockout Hysteresis Internal Regulator Voltage INTVCC Undervoltage Lockout INTVCC Undervoltage Lockout Hysteresis Circuit Breaker Threshold (VDD - VSENSE) Current Limit Voltage (VDD - VSENSE) VFB = 1.3V VFB = 0V Start-Up Timer Expired VSENSE = 50mV VSENSE = 12V VDD 3.3V INTVCC Rising VDD Rising

ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN 2.9 15 2.75 75 2.9 2.55 20 22.5 22 6.5 65 15 10 4.7 -15 0.8 300
TYP
MAX 15
UNITS V V mA V mV V V mV mV mV mV mV s A V A mA mA s V V mV A V mV A V mV A V mV A V mV V
4215fb
15.6 3 2.84 100 3.1 2.64 55 25 25 10 75 20 20 5.9 -20 1 450 0.5
16.5 5 2.89 125 3.4 2.79 75 27.5 29 13 90 30 35 6.5 -30 1.6 700 1 4.7 1.26 180 1 1.255 200 1 1.255 40 1 1.255 100 1 0.47 210 1.255
Current Limit and Circuit Breaker

tD(OC) ISENSE(IN) Gate Drive VGATE IGATE(UP) IGATE(DN)SLOW IGATE(DN)FAST tPHL(SENSE) VGS(POWERBAD) VON(TH) VON(HYST) ION(IN) VEN(TH) VEN(HYST) IEN VOV(TH) VOV(HYST) IOV(IN) VUV(TH) VUV(HYST) IUV(IN) VUV(RTH) VUV(RHYST) VFB
OC Fault Filter SENSE Pin Input Current
External N-Channel Gate Drive (VGATE - VSOURCE) VDD = 2.9V to 15V (Note 3) External N-Channel Gate Pull-Up Current Gate On, VGATE = 0V External N-Channel Gate Pulldown Current Pulldown Current From GATE to SOURCE During OC/UVLO (VDD - SENSE) High to GATE Low Gate-Source Voltage for Power Bad Fault ON Pin Threshold Voltage ON Pin Hysteresis ON Pin Input Current EN Input Threshold EN Hysteresis EN Pin Input Current OV Pin Threshold Voltage OV Pin Hysteresis OV Pin Input Current UV Pin Threshold Voltage UV Pin Hysteresis UV Pin Input Current UV Pin Reset Threshold Voltage UV Pin Reset Threshold Hysteresis Foldback Pin Power Good Threshold FB Rising VUV = 1.8V VUV Falling VOV = 1.8V VUV Rising EN = 3.5V VOV Rising VON = 1.2V VEN = Rising Gate Off, VGATE = 15V VDD - SENSE = 100mV, VGS = 4V VDD - SENSE = 100mV, CGS = 10nF VSOURCE = 2.9V - 15V VON Rising

3.8 1.210 60 1.215 50 1.215 10 1.215 60 0.33 60 1.215
4.3 1.235 128 0 1.235 128 0 1.235 30 0 1.235 80 0 0.4 125 1.235
Comparator Inputs

3
LTC4215
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 12V unless otherwise noted.
SYMBOL VFB(HYST) IFB VGPIO(TH) VGPIO(OL) IGPIO(OH) ISOURCE tP(GATE) tD(GATE) PARAMETER FB Pin Power Good Hysteresis Foldback Pin Input Current GPIO Pin Input Threshold GPIO Pin Output Low Voltage GPIO Pin Input Leakage Current SOURCE Pin Input Current Input (ON, OV, UV, EN) to GATE Off Propagation Delay Turn-On Delay FB = 1.8V VGPIO Rising IGPIO = 5mA VGPIO = 15V SOURCE = 15V CONDITIONS

ELECTRICAL CHARACTERISTICS
MIN 3
TYP 8 0
MAX 15 1 1.2 0.5 1 120 5 2 150 75 0.23 1.26 -120 2.6 60 -12.5 -1.0
UNITS mV A V V A A s s ms s V V A A A A A Bits
0.8
1 0.25 0
Other Pin Functions

40
80 3 1 100 5 0.2 1.235 -100 2 50 -10 -0.7
ON UV, OV, EN Overcurrent Auto-Retry

VTIMERL(TH) VTIMERH(TH) ITIMER(UP) ITIMER(DOWN) ISS ADC
Timer Low Threshold Timer High Threshold TIMER Pin Pull-Up Current TIMER Pin Pulldown Current for OC Auto-Retry Soft-Start Ramp Pull-Up Current Ramping Waiting for GATE to Slew
50 2.5 0.17 1.2 -80 1.4 40 -7.5 -0.4 8 -2 -1.25 -1.25
ITIMER(UP/DOWN) TIMER Current Up/Down Ratio

Resolution (No Missing Codes) Integral Nonlinearity VDD - SENSE (Note 5) SOURCE ADIN VDD - SENSE SOURCE ADIN VDD - SENSE SOURCE ADIN VDD - SENSE SOURCE ADIN VDD - SENSE SOURCE ADIN VADIN = 1.28V VADIN = 1.28V

0.5 0.2 0.2
Offset Error (Note 4)
Total Unadjusted Error
Full-Scale Error
Full-Scale Voltage (255 * VLSB)
RADIN IADIN I2C Interface VADR(H) IADR(IN,Z) VADR(L) IADR(IN)
ADIN Pin Sampling Resistance ADIN Pin Input Current Conversion Rate ADR0, ADR1, ADR2 Input High Voltage ADR0, ADR1, ADR2 Hi-Z Input Current ADR0, ADR1, ADR2 Input Low Voltage ADR0, ADR1, ADR2 Input Current
37.625 15.14 1.205 1
38.45 15.44 1.23 2 0 10
2 1.25 1.25 2.0 1.0 1.0 5.5 5.0 5.0 5.5 5.0 5.0 39.275 15.74 1.255 0.1
LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB mV V V M A Hz
INTVCC -0.8 3 0.2 -80
INTVCC -0.4
ADR0, ADR1, ADR2 = 0.8V ADR0, ADR1, ADR2 = INTVCC - 0.8V ADR0, ADR1, ADR2 = 0V, INTVCC

INTVCC -0.2 -3 0.8 80
V A A V A
4215fb
0.4
4
LTC4215
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 12V unless otherwise noted.
SYMBOL IALERT VALERT(OL) VSDA,SCL(TH) ISDA,SCL(OH) VSDA(OL) fSCL(MAX) tBUF(MIN) tHD,STA(MIN) tSU,STA(MIN) tSU,STO(MIN) tHD,DAT(MIN) tHD,DATO tSU,DAT(MIN) tSP CX PARAMETER ALERT Input Current ALERT Output Low Voltage SDA, SCL Input Threshold SDA, SCL Input Current SDA Output Low Voltage SCL Clock Frequency Bus Free Time Between Stop/Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Set-Up Time Stop Condition Set-Up Time Data Hold Time (Input) Data Hold Time (Output) Data Set-Up Time Suppressed Spike Pulse Width SCL, SDA Input Capacitance SDAI Tied to SDAO SCL, SDA = 6.5V ISDA = 3mA Operates with fSCL fSCL(MAX) CONDITIONS ALERT = 6.5V IALERT = 3mA

ELECTRICAL CHARACTERISTICS
MIN
TYP 0.2
MAX 1 0.4 1.9 1 0.4
UNITS A V V A V kHz
1.3
1.7 0.2
I2C Interface Timing

400
1000 0.12 30 30 140 30 1.3 600 600 600 100 900 600 250 10
s ns ns ns ns ns ns ns pF
300 50
500 30 110
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a minimum of 5V above SOURCE. Driving this pin to voltages beyond the clamp may damage the device.
Note 4: Offset error is the offset voltage measured from 1LSB when the output code flickers between 0000 0000 and 0000 0001. Note 5: Integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size and the single shot measurement. Typical specifications are measured from the 1/4, 1/2 and 3/4 areas of the quantization band.
TYPICAL PERFOR A CE CHARACTERISTICS
IDD vs VDD
4 4.0
3 3.5 IDD (mA) VDD (V) VCC (V) 2
1
0 0 5 15 10 VDD (V) 20 25
4215 G01
UW
TA = 25C, VDD = 12V unless otherwise noted INTVCC vs ILOAD
4 VDD = 12V, 5V 3 VDD = 3.3V 2
INTVCC vs VDD
3.0 1
2.5 2.5 3.0 INTVCC (V)
4215 G02
0 3.5 4.0 0 2 6 4 ILOAD (mA) 8 10
4215 G03
4215fb
5
LTC4215 TYPICAL PERFOR A CE CHARACTERISTICS
VTH(UV) vs Temperature
1.240 90
1.238 VTH (UV) RISING (V) VHYST(UV) (mV)
1.236
ITIMER (A) 100
4215 G05
1.234
1.232
1.230 -50
-25
50 25 0 TEMPERATURE (C)
Current Limit vs VFB
30 CIRCUIT BREAKER THRESHOLD (mV) 25 20 ILIM (mV) 15 10 5 0 27
25
VDD = 3.3V
VGATE(SOURCE) (V)
0
0.2
0.4
0.6
0.8
1.0
VFB (V)
4215 G07
VGATE vs IGATE
7 6 5 VGATE (V) 4 3 2 1 0 0 5 10 15 20 25
4215 G10
VDD = 5V -25 VOL(GPIO) (V) VDD = 12V IGATE (A) VDD = 3.3V -20
IGATE (A)
6
UW
75 1.2
TA = 25C, VDD = 12V unless otherwise noted ITIMER vs Temperature
110
VHYST(UV) vs Temperature
85
105
80
100
75
95
100
4215 G04
70 -50
-25
50 25 0 TEMPERATURE (C)
75
90 -50
-25
50 25 0 TEMPERATURE (C)
75
100
4215 G06
VTH Circuit Breaker vs Temperature
6.1 6.0 26 VDD = 5V, 12V 5.9 5.8 5.7
VGATE vs Temperature
VDD = 5V VDD = 12V
24
VDD = 3.3V 5.6 5.5
23
1.4
22 -50
-25
50 25 0 TEMPERATURE (C)
75
100
4215 G08
5.4 -50
-25
0
25
50
75
100
4215 G09
TEMPERATURE (C)
IGATE Pull-Up vs Temperature
-30 0.6 0.5 0.4
VOL(GPIO) vs IGPIO
VDD = 3.3V, 5V, 12V 0.3 0.2
-15 0.1 -10 -50 0 -25 50 25 0 TEMPERATURE (C) 75 100
4315 G11
0
2
4 6 IGPIO (mA)
8
10
4215 G12
4215fb
LTC4215 TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error vs Code (ADIN)
0.006 0.005 0.004 ERROR (V) INL (LSB) 0.003 0.002 0.001 0 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 64 128 CODE 192 256
4215 G13
ADC DNL vs Code (ADIN)
0.5 0.4 FULL-SCALE ERROR (LSB) 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 64 128 CODE 192 256
4215 G15
PI FU CTIO S
ADIN (QFN Package): ADC Input. A voltage between 0V and 1.235V applied to this pin is measured by the onboard ADC. Tie to ground if unused. ADR0, ADR1, ADR2 (ADR1, ADR2 Available in QFN Package): Serial Bus Address Inputs. Tying these pins to ground, to the INTVCC pin or open configures one of 27 possible addresses. See Table 1 in Applications Information. A L E RT: Fault Alert Output. Open-drain logic output that is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the A L E RT register. See Applications Information. Tie to ground if unused. EN: (QFN package) Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn on. When this pin is high, the MOSFET is not allowed to turn on. An internal 10A current source pulls up this pin. Transitions on this pin are recorded in the Fault register. A high-to-low transition activates the logic to read the state of the ON pin and clear Faults. See Applications Information.
4215fb
UW
TA = 25C, VDD = 12V unless otherwise noted
ADC INL vs Code (ADIN)
0
64
128 CODE
192
256
4215 G14
ADC Full-Scale Error vs Temperature
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 50 25 0 TEMPERATURE (C) 75 100
4215 G05
U
U
U
7
LTC4215 PI FU CTIO S
EXPOSED PAD (Pin 25, QFN Package): Exposed Pad may be left open or connected to device ground. FB: Foldback Current Limit and Power Good Input. A resistive divider from the output is tied to this pin. When the voltage at this pin drops below 1.235V, power is not considered good. The power bad condition may result in the GPIO pin pulling low or going high impedance depending on the configuration of control register bits A6 and A7. Also a power bad fault is logged in this condition if the LTC4215 has finished the start-up cycle and the GATE pin is high. See Applications Information. The start-up current limit folds back linearly from 25mV sense voltage at 0.6V to 10mV at 0.2V on the FB pin. Foldback is not active once the part leaves start-up and the current limit is increased to 75mV. GATE: Gate Drive for External N-Channel MOSFET. An internal 20A current source charges the gate of the MOSFET. No compensation capacitor is required on the GATE pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output voltage slew rate. During turn-off there is a 1mA pulldown current. During a short circuit or undervoltage lockout (VDD or INTVCC), a 450mA pulldown current source between GATE and SOURCE is activated. GND: Device Ground. GPIO: General Purpose Input/Output. Open-drain logic output or logic input. Defaults to an output set to pull low to indicate power is not good. Configure according to Table 2. INTVCC: Low Voltage Supply Decoupling Output. Connect a 0.1F capacitor from this pin to ground. ON: On Control Input. A rising edge turns on the external N-channel MOSFET and a falling edge turns it off. This pin also configures the state of the FET On bit in the control register (and hence the external MOSFET) at power up. For example, if the ON pin is tied high, then the FET On bit (A3 in Table 2) goes high 100ms after power-up. Likewise if the ON pin is tied low then the part remains off after power-up until the FET On bit is set high using the I2C bus. A high-to-low transition on this pin clears the fault register. OV (QFN Package): Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 1.235V, an overvoltage fault is detected and the GATE turns off. Tie to GND if unused. SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open-collector output from a master controller. An external pull-up resistor or current source is required. SDAO (QFN Package): Serial Bus Data Output. Open-drain output for sending data back to the master controller or acknowledging a write operation. Normally tied to SDAI to form the SDA line. An external pull-up resistor or current source is required. Internally tied to SDAI in SSOP package. SDAI: Serial Bus Data Input. A high impedance input for shifting in address, command or data bits. Normally tied to SDAO to form the SDA line. Internally tied to SDAO in SSOP package. SDA (SSOP Package): Serial Bus Data Input/Output Line. Formed by internally tying the SDAO and SDAI lines together. An external pull-up resistor or current source is required. SENSE+ (QFN Package): Positive Current Sense Input. Connect this pin to the input of the current sense resistor. Must be connected to the same trace as VDD. Internally tied to VDD in SSOP package. SENSE-: Negative Current Sense Input. Connect this pin to the output of the current sense resistor. The current limit circuit controls the GATE pin to limit the sense voltage between the SENSE and VDD pins to 25mV or less. SOURCE: N-Channel MOSFET Source and ADC Input. Connect this pin to the source of the external N-channel MOSFET switch for gate drive return. This pin also serves as the ADC input to monitor output voltage. The pin provides a return for the gate pulldown circuit. SS: Sets the inrush current slew rate at start-up. Connect a 68nF capacitor to provide 5mV/ms as the slew rate for the sense voltage in start-up. This corresponds to 1A/ms with a 5m sense resistor. Note that a large soft-start capacitor and a small TIMER capacitor may result in a condition where the timer expires before the inrush current has started. Allow an additional 10nF of timer capacitance
4215fb
8
U
U
U
LTC4215 PI FU CTIO S
per 1nF of soft-start capacitor to ensure proper start-up. Use 1nF minimum to ensure an accurate inrush current. TIMER: Start-Up Timer Input. Connect a capacitor between this pin and ground to set a 12.3ms/F duration for start-up, after which an overcurrent fault is logged if the inrush is still current limited. The duration of the off time is 600ms/F when overcurrent auto-retry is enabled, resulting in a 1:50 duty cycle. An internal timer provides a 100ms start-up time and 5 seconds auto-retry time if this pin is tied to INTVCC. Allow an additional 10nF of timer capacitance per 1nF of soft-start (SS) capacitor to ensure proper start-up. The minimum value for the TIMER capacitor is 10nF. UV: Undervoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin falls below 1.227V, an undervoltage fault is detected and the GATE turns off. Pulling this pin below 0.4V resets all faults and allows the GATE to turn back on. Tie to INTVCC if unused. VDD: Supply Voltage Input. This pin has an undervoltage lockout threshold of 2.84V and overvoltage lockout threshold of 15.6V.
FU CTIO AL DIAGRA
VCC 10A SS FB 1.235V UV
1.235V 0.6V
+ - -+
+-
FAULT PG
+ - + - + - + - + - + - + -
UV
UV 1.235V
0.4V
RST RESET
+ -
PWRGD
OV (QFN) INTVCC EN (QFN) ON 1.235V 2.84V VDD 1.235V 10A 1.235V
OV1
OV LOGIC
EN
EN TM1
ON
ON TM2
+ - + -
0.2V 100A TIMER 2A 1.235V UVLO2 3.1V GEN
UVLO1 VDD(UVLO)
OV2
OV2
15.6V ADIN (QFN) SDAI (QFN) SDAO (QFN) SDA (SSOP) SCL
A/D CONVERTER 8 SOURCE VDD - VSENSE
I2C
I2C ADDR 5 1 OF 27
ALERT
+ -
W
U
U
U
U
U
SENSE-
SENSE+ (QFN), VDD (SSOP) GATE CHARGE PUMP AND GATE DRIVER SOURCE
FOLDBACK AND dI/dt
CB
CS
FET ON
GP
+ -
GPI0 1V
+ -
INTVCC 2.64V
ADRO ADR1 (QFN) ADR2 (QFN)
4215 BD
4215fb
9
LTC4215 TI I G DIAGRA
SDAI/SDAO tSU, DAT tHD, DATO, tHD, DATI tSU, STA tSP tHD, STA tSP tBUF tSU, STO
4215 TD01
SCL tHD, STA START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION
OPERATIO
The LTC4215 is designed to turn a board's supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate driver turn on an external N-channel MOSFET's gate to pass power to the load. The gate driver uses a charge pump that derives its power from the VDD pin. Also included in the gate driver is an internal 6.5V GATE-to-SOURCE clamp. During start-up the inrush current is tightly controlled by using current limit foldback, soft start dI/dt limiting and output dV/dt limiting. The current sense (CS) amplifier monitors the load current using the difference between the SENSE+ (VDD for SSOP) and SENSE- pin voltages. The CS amplifier limits the current in the load by pulling back on the GATE-to-SOURCE voltage in an active control loop when the sense voltage exceeds the commanded value. The CS amplifier requires 20A input bias current from both the SENSE+ and the SENSE- pins. A short circuit on the output to ground results in excessive power dissipation during active current limiting. To limit this power, the CS amplifier regulates the voltage between the SENSE+ and SENSE- pins at 75mV. If an overcurrent condition persists, the internal circuit breaker (CB) registers a fault when the sense voltage exceeds 25mV for more than 20s. This indicates to the logic that it is time to turn off the GATE to prevent overheating. At this point the start-up TIMER pin voltage ramps down using the 2A current source until the voltage drops below 0.2V (comparator TM1) which tells the logic that the pass transistor has cooled and it is safe to turn it on again if
10
W
overcurrent auto-retry is enabled. If the TIMER pin is tied to INTVCC, the cool-down time defaults to 5 seconds on an internal system timer in the logic. The output voltage is monitored using the FB pin and the Power Good (PG) comparator to determine if the power is available for the load. The power good condition can be signaled by the GPIO pin using an open-drain pulldown transistor. The GPIO pin may also be configured to signal power bad, or as a general purpose input (GP comparator), or a general purpose open drain output. The Functional Diagram shows the monitoring blocks of the LTC4215. The group of comparators on the left side includes the undervoltage (UV), overvoltage (OV), reset (RST), enable (EN) and signal on (ON) comparators. These comparators determine if the external conditions are valid prior to turning on the GATE. But first the two undervoltage lockout circuits, UVLO1 and UVLO2, validate the input supply and the internally generated 3.1V supply, INTVCC. UVLO2 also generates the power-up initialization to the logic circuits as INTVCC crosses this rising threshold. If the fixed internal overvoltage comparator, OV2, detects that VDD is greater than 15.6V, the part immediately generates an overvoltage fault and turns the GATE off. Included in the LTC4215 is an 8-bit A/D converter. The converter has a 3-input multiplexer to select between the ADIN pin, the SOURCE pin and the VDD - SENSE voltage. An I2C interface is provided to read the A/D registers. It also allows the host to poll the device and determine if faults have occurred. If the ALERT line is configured as an interrupt, the host is enabled to respond to faults in real time. The typical SDA line is divided into an SDAI (input)
4215fb
U
UW
LTC4215 OPERATIO
and SDAO (output). This simplifies applications using an optoisolator driven directly from the SDAO output. An application which uses optoisolation is shown in Figure 14. The I2C device address is decoded using the ADR0,
APPLICATIO S I FOR ATIO
A typical LTC4215 application is in a high availability system in which a positive voltage supply is distributed to power individual cards. The device measures card voltages and currents and records past and present fault conditions. The system queries each LTC4215 over the I2C periodically and reads status and measurement information. A basic LTC4215 application circuit is shown in Figure 1. The following sections cover turn-on, turn-off and various faults that the LTC4215 detects and acts upon. External component selection is discussed in detail in the Design Example section. Turn-On Sequence The power supply on a board is controlled by using an external N-channel pass transistor (Q1) placed in the power path. Note that resistor RS provides current detection. Resistors R1, R2 and R3 define undervoltage and overvoltage levels. R5 prevents high frequency oscillations in Q1 and R6 and C1 form an optional network that may be used to provide an output dV/dt limited start-up.
VIN 12V Z1 SA14A CONNECTOR 2 CONNECTOR 1 CF 0.1F R1 34k 1% R2 1.02k 1% R3 3.4k 1%
SDA SCL ALERT
GND BACKPLANE PLUG-IN CARD
Figure 1. Typical Application
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ADR1 and ADR2 pins. These inputs have three states each that decode into a total of 27 device addresses. ADR1 and ADR2 are not available in the SSOP package; therefore, those pins are NC in the address map. Several conditions must be present before the external MOSFET turns on. First the external supply, VDD, must exceed its 2.84V undervoltage lockout level. Next the internally generated supply, INTVCC, must cross its 2.64V undervoltage threshold. This generates a 60s to 120s power-on-reset pulse. During reset the fault registers are cleared and the control registers are set or cleared as described in the register section. After a power-on-reset pulse, the LTC4215 goes through the following turn-on sequence. First the UV and OV pins indicate that input power is within the acceptable range, which is indicated by bits C0-C1 in Table 4. Second, the EN pin is externally pulled low. Finally, all of these conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during insertion has ended. When these initial conditions are satisfied, the ON pin is checked and it's state written to bit A3 in Table 2. If it is high, the external MOSFET is turned on. If the ON pin is low, the external MOSFET is turned on when the ON pin
RS 0.005 Q1 FDC653N R7 30.1k 1% R8 3.57k 1% VOUT 12V CL 330F
+
R4 24k
R5 10
R6 15k C1 6.8nF
UV VDD SENSE+ SENSE- GATE OV ON SDAI LTC4215UFD SDAO SCL ALERT
SOURCE FB ADIN GPIO EN SS CSS 7.5nF
TIMER INTVCC ADR0 ADR1 ADR2 GND CTIMER 0.68F C3 0.1F NC
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LTC4215 APPLICATIO S I FOR ATIO
is brought high or if a serial bus turn-on command is sent by setting bit A3. The MOSFET is turned on by charging up the GATE with a 20A current source. When the GATE voltage reaches the MOSFET threshold voltage, the MOSFET begins to turn on and the SOURCE voltage then follows the GATE voltage as it increases. When the MOSFET is turning on, it ramps inrush current up linearly at a dI/dt rate selected by capacitor CSS. Once the inrush current reaches the limit set by the FB pin, the dI/dt ramp stops and the inrush current follows the foldback profile as shown in Figure 2. The TIMER pin integrates at 100A during start-up and once it reaches its threshold of 1.235V, the part checks to see if it is in current limit, which indicates that it has started up into a short-circuit condition. If this is the case, the overcurrent fault bit, D2 in Table 5, is set and the part turns off. If the part is not in current limit, the 25mV circuit breaker is armed and the current limit is switched to 75mV. Alternately an internal 100ms start-up timer may be selected by tying the TIMER pin to INTVCC. As the SOURCE voltage rises, the FB pin follows as set by R7 and R8. Once FB crosses its 1.235V threshold, and the start-up timer has expired, the GPIO pin, in its default configuration, ceases to pull low and indicates that power is now good.
VDD + 6V VGATE
VDD
VOUT GPIO (POWER GOOD)
VSENSE 25mV
10mV ILOAD * RSENSE
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SS LIMITED
FB LIMITED
TIMER EXPIRES
Figure 2. Power-Up Waveforms
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If R6 and C1 are employed for a constant current during start-up, which produces a constant dV/dt at the output, a 20A pull-up current from the gate pin slews the gate upwards and the part is not in current limit. The start-up TIMER may expire in this condition and an OC fault is not generated even though start-up has not completed. Either the sense voltage increases to the 25mV CB threshold and generates an OC fault, or the FB pin voltage crosses its 1.235V power good threshold and the GPIO pin signals power good. GATE Pin Voltage A curve of GATE-to-SOURCE drive vs VDD is shown in the Typical Performance Characteristics. At minimum input supply voltage of 2.9V, the minimum GATE-to-SOURCE drive voltage is 5V. The GATE-to-SOURCE voltage is clamped below 6.5V to protect the gates of logic level N-channel MOSFETs. Turn-Off Sequence The GATE is turned off by a variety of conditions. A normal turn-off is initiated by the ON pin going low or a serial bus turn-off command. Additionally, several fault conditions turn off the GATE. These include an input overvoltage (OV pin), input undervoltage (UV pin), overcurrent circuit breaker (SENSE- pin), or EN transitioning high. Writing a logic one into the UV, OV or OC fault bits (D0-D2 in Table 5) also latches off the GATE if their auto-retry bits are set to false. Normally the MOSFET is turned off with a 1mA current pulling down the GATE pin to ground. With the MOSFET turned off, the SOURCE and FB voltages drop as CL discharges. When the FB voltage crosses below its threshold, GPIO pulls low to indicate that the output power is no longer good. If the VDD pin falls below 2.74V for greater than 2s or INTVCC drops below 2.60V for greater than 1s, a fast shut down of the MOSFET is initiated. The GATE pin is pulled down with a 450mA current to the SOURCE pin. Overcurrent Fault The LTC4215 features an adjustable current limit that protects against short circuits or excessive load current.
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LTC4215 APPLICATIO S I FOR ATIO
An overcurrent fault occurs when the circuit breaker 25mV threshold has been exceeded for longer than the 20s timeout delay. Current limiting begins immediately when the current sense voltage between the VDD and SENSE pins reaches 75mV. The GATE pin is then brought down and regulated in order to limit the current sense voltage to 75mV. When the 20s circuit breaker time out has expired, the overcurrent present bit C2 is set. The external MOSFET is turned off and the overcurrent fault bit D2 is set at this time. After the MOSFET is turned off, the TIMER capacitor begins discharging with a 2A pulldown current. When the TIMER pin reaches its 0.2V threshold the MOSFET is allowed to turn on again if the overcurrent fault has been cleared. However, if the overcurrent auto-retry bit, A2 has been set then the MOSFET turns on again automatically without resetting the overcurrent fault. Use a minimum value of 10nF for CT. If the TIMER pin is bypassed by tying it to INTVCC, the part is allowed to turn on again after an internal 5 second timer has expired, in the same manner as the TIMER pin passing its 0.2V threshold.
VGATE 10V/DIV VSOURCE 10V/DIV VDD 10V/DIV
ILOAD 10A/DIV
RS = 5m CL = 0 RSHORT = 1 R6 = 30k C1 = 0.1F
5s/DIV
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Figure 3. Short-Circuit Waveforms
Overvoltage Fault An overvoltage fault occurs when either the OV pin rises above its 1.235V threshold, or the VDD pin rises above its 15.6V threshold, for more than 2s. This shuts off the GATE with a 1mA current to ground and sets the overvoltage present bit C0 and the overvoltage fault bit D0. If the pin subsequently falls back below the threshold for 100ms, the GATE is allowed to turn on again unless overvoltage auto-retry has been disabled by clearing bit A0.
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Undervoltage Fault An undervoltage fault occurs when the UV pin falls below its 1.235V threshold for more than 2s. This turns off the GATE with a 1mA current to ground and sets undervoltage present bit C1 and undervoltage fault bit D1. If the UV pin subsequently rises above the threshold for 100ms, the GATE is turned on again unless undervoltage auto-retry has been disabled by clearing bit A1. When power is applied to the device, if UV is below its 1.235V threshold after INTVCC crosses its 2.64V undervoltage lockout threshold, an undervoltage fault is logged in the fault register. Board Present Change of State Whenever the EN pin toggles, bit D4 is set to indicate a change of state. When the EN pin goes high, indicating board removal, the GATE turns off immediately (with a 1mA current to ground) and clears the board present bit, C4. If the EN pin is pulled low, indicating a board insertion, all fault bits except D4 are cleared and enable bit, C4, is set. If the EN pin remains low for 100ms the state of the ON pin is captured in `FET On' control bit A3. This turns the switch on if the ON pin is tied high. There is an internal 10A pull-up current source on the EN pin. If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4215 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the EN pin detects when the plug-in card is removed. Figure 4 shows an example where the EN pin is used to detect insertion. Once the plug-in card is reinserted the fault register is cleared (except for D4). After 100ms the state of the ON pin is latched into bit A3 of the control register. At this point the system starts up again. If a connection sense on the plug-in card is driving the EN pin, insertion or removal of the card may cause the pin voltage to bounce. This results in clearing the fault register when the card is removed. The pin may be debounced using a filter capacitor, CEN, on the EN pin as shown in Figure 4. The filter time is given by: tFILTER = CEN * 123 (ms/F)
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LTC4215 APPLICATIO S I FOR ATIO
OUT LTC4215 SOURCE
+ -
GND 1.235V
EN CEN
MOTHERBOARD
CONNECTOR
Figure 4. Plug-In Card Insertion/Removal
FET Short Fault A FET short fault is reported if the data converter measures a current sense voltage greater than or equal to 1.6mV while the GATE is turned off. This condition sets FET short present bit, C5, and FET short fault bit D5. Power Bad Fault A power bad fault is reported if the FB pin voltage drops below its 1.235V threshold for more than 2s when the GATE is high. This pulls the GPIO pin low immediately when configured as power-good, and sets power-bad present bit, C3, and power bad fault bit D3. A circuit prevents power-bad faults if the GATE-to-SOURCE voltage is low, eliminating false power-bad faults during power-up or power-down. If the FB pin voltage subsequently rises back above the threshold, the GPIO pin returns to a high impedance state and bit C3 is reset. Fault Alerts When any of the fault bits in FAULT register D are set, an optional bus alert is generated if the appropriate bit in the ALERT register B has been set. This allows only selected faults to generate alerts. At power-up the default state is to not alert on faults. If an alert is enabled, the corresponding fault causes the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4215 responds with its address on the SDA line and releases ALERT as shown in Table 6. If there is a collision
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between two LTC4215s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds first. The ALERT line is also released if the device is addressed by the bus master.
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Once the ALERT signal has been released for one fault, it is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated FAULT register bit has been cleared. Resetting Faults Faults are reset with any of the following conditions. First, a serial bus command writing zeros to the FAULT register D clears the associated faults. Second, the entire FAULT register is cleared when the switch is turned off by the ON pin or bit A3 going from high to low, if the UV pin is brought below its 0.4V reset threshold for 2s, or if INTVCC falls below its 2.64V undervoltage lockout threshold. Finally, when EN is brought from high to low, only FAULT bits D0-D3 are cleared, and bit D4, that indicates a EN change of state, is set. Note that faults that are still present, as indicated in STATUS Register C, cannot be cleared. The FAULT register is not cleared when auto-retrying. When auto-retry is disabled the existence of a D0, D1 or D2 fault keeps the switch off. As soon as the fault is cleared, the switch turns on. If auto-retry is enabled, then a high value in C0, C1 or C2 holds the switch off and the fault register is ignored. Subsequently, when bits C0, C1 and C2 are cleared by removal of the fault condition, the switch is allowed to turn on again. Data Converter The LTC4215 incorporates an 8-bit A/D converter that continuously monitors three different voltages. The SOURCE pin has a 1/12.5 resistive divider to monitor a full scale voltage of 15.4V with 60mV resolution. The ADIN pin is monitored with a 1.235V full scale and 4.82mV resolution, and the voltage between the VDD and SENSE pins is monitored with a 38.6mV full scale and 151V resolution. Results from each conversion are stored in registers E (Sense), F (Source) and G (ADIN), as seen in Tables 6-8,
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LTC4215 APPLICATIO S I FOR ATIO
and are updated 10 times per second. Setting CONTROL register bit A5 invokes a test mode that halts the data converter so that registers E, F, and G may be written to and read from for software testing. Configuring the GPIO Pin Table 2 describes the possible states of the GPIO pin using the control register bits A6 and A7. At power-up, the default state is for the GPIO pin to go high impedance when power is good (FB pin greater than 1.235V). Other applications for the GPIO pin are to pull down when power is good, a general purpose output and a general purpose input. Supply Transients The LTC4215 is designed to ride through supply transients caused by load steps. If there is a shorted load and the parasitic inductance back to the supply is greater than 0.5H, there is a chance that the supply collapses before the active current limit circuit brings down the GATE pin. If this occurs, the undervoltage monitors pull the GATE pin low. The undervoltage lockout circuit has a 2s filter time after VDD drops below 2.74V. The UV pin reacts in 2s to shut the GATE off, but it is recommended to add a filter capacitor CF to prevent unwanted shutdown caused by a transient. Eventually either the UV pin or undervoltage lockout responds to bring the current under control before the supply completely collapses. Supply Transient Protection The LTC4215 is safe from damage with supply voltages up to 24V. However, spikes above 24V may damage the part. During a short-circuit condition, large changes in current flowing through power supply traces may cause inductive voltage spikes which exceed 24V. To minimize such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Also, a snubber circuit dampens inductive voltage spikes. Build a snubber by using a 100 resistor in series with a 0.1F capacitor between VDD and GND. A surge suppressor, Z1 in Figure 1, at the input can also prevent damage from voltage surges. PDISS =
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Design Example As a design example, take the following specifications: VIN = 12V, IMAX = 5A, IINRUSH = 1A, dI/dtINRUSH = 10A/ms, CL = 330F, VUV(ON) = 10.75V, VOV(OFF) = 14.0V, VPWRGD(UP) = 11.6V, and I2C ADDRESS = 1010011. This completed design is shown in Figure 1. Selection of the sense resistor, RS, is set by the overcurrent threshold of 25mV: RS = 25mV = 0.005 IMAX The MOSFET is sized to handle the power dissipation during inrush when output capacitor COUT is being charged. A method to determine power dissipation during inrush is based on the principle that: Energy in CL = Energy in Q1 This uses:
2 Energy in CL = 1 CV 2 = 1 (0.33mF)(12) 2 2
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or 0.024 joules. Calculate the time it takes to charge up COUT: V 12V tCHARGEUP = CL * DD = 0.33mF * = 4ms IINRUSH 1A The power dissipated in the MOSFET: Energyin CL = 6W tCHARGEUP
The SOA (safe operating area) curves of candidate MOSFETs must be evaluated to ensure that the heat capacity of the package tolerates 6W for 4ms. The SOA curves of the Fairchild FDC653N provide for 2A at 12V (24W) for 10ms, satisfying this requirement. The inrush current is set to 1A using C1: C1 = CL * IGATE IINRUSH 20A or C1 = 6.8nF 8 1A
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LTC4215 APPLICATIO S I FOR ATIO
The inrush dI/dt is set to 10A/ms using CSS: CSS = ISS 1 * 0.0375 * RSENSE dI / dt A s 10A * 0.0375 * 1 = 7.5nF 5m 10000
=
For a start-up time of 4ms with a 2x safety margin we choose: t CTIMER = 2 * STARTUP + CSS * 10 12.3ms/F CTIMER = 8ms + 7.5nF * 10 0.68F 12.3ms/F
Note the minimum value of CTIMER is 10nF, and each 1nF of soft-start capacitance needs 10nF of TIMER capacitance/time during start-up.
GATE UV OV R3 SS GND ON EN ALERT SDAO SDAI SCL ADR0 LTC4215UFD SOURCE VDD SENSE+ SENSE-
Choose R1, R2, R3, R7 and R8 for the UV, OV and PG threshold voltages: VOV(RISING) = 14.0V, VOV(FALLING) = 13.5V (using VOV(TH) = 1.235 rising and 1.185V falling) VUV(RISING) = 10.75V, VUV(FALLING) = 10.6V (using VUV(TH) = 1.235V rising and 1.215V falling) VPG(RISING) = 11.6V, VPG(FALLING) = 10.85V (using VFB(TH) = 1.235V rising and 1.155V falling) A 0.1F capacitor, CF, is placed on the UV pin to prevent supply glitches from turning off the GATE via UV or OV. The address is set with the help of Table 1, which indicates binary address 1010011 corresponds to address 19. Address 19 is set by setting ADR2 high, ADR1 open and ADR0 high. Next the value of R5 and R6 are chosen to be the default values 10 and 15k as discussed previously. In addition a 0.1F ceramic bypass capacitor is placed on the INTVCC pin. Layout Considerations To achieve accurate current sensing, a Kelvin connection is required. The minimum trace width for 1oz copper
ILOAD
NC
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foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530/(R). Small resistances add up quickly in high current applications. To improve noise immunity, put the resistive dividers to the UV, OV and FB pins close to the device and keep traces to VDD and GND short. It is also important to put the bypass capacitor for the INTVCC pin, C3, as close as possible between INTVCC and GND. A 0.1F capacitor from the UV pin (and OV pin through resistor R2) to GND also helps reject supply noise. Figure 4 shows a layout that addresses these issues. Note that a surge suppressor, Z1, is placed between supply and ground using wide traces.
SENSE RESISTOR RS ILOAD R1 Z1 FB GPIO R8 CF R2 C3 INTVCC TIMER ADIN ADR2 ADR1
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Figure 5. Recommended Layout
Digital Interface The LTC4215 communicates with a bus master using a 2-wire interface compatible with I2C Bus and SMBus, an I2C extension for low power devices. The LTC4215 is a read-write slave device and supports SMBus bus Read Byte, Write Byte, Read Word and Write Word commands. The second word in a Read Word command is identical to the first word. The second word in a Write Word command is ignored. Data formats for these commands are shown in Figures 6 to 11.
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LTC4215 APPLICATIO S I FOR ATIO
SDA a6 - a0
SCL S
1-7
8
9
START CONDITION
ADDRESS
R/W
ACK
Figure 6. Data Transfer Over I2C or SMBus
START and STOP Conditions When the bus is idle, both SCL and SDA are high. A bus master signals the beginning of a transmission with a start condition by transitioning SDA from high to low while SCL is high, as shown in Figure 6. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. I2C Device Addressing Twenty-seven distinct bus addresses are available using three 3-state address pins, ADR0-ADR2. Table 1 shows the correspondence between pin states and addresses. Note that address bits B7 and B6 are internally configured to 10. In addition, the LTC4215 responds to two special addresses. Address (1011 111) is a mass write address that writes to all LTC4215s, regardless of their individual address settings. Mass write can be disabled by setting register A4 to zero. Address (0001 100) is the SMBus Alert Response Address. If the LTC4215 is pulling low on the ALERT pin, it acknowledges this address by broadcasting its address and releasing the ALERT pin. Acknowledge The acknowledge signal is used in handshaking between transmitter and receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. When the slave is the receiver, it pulls down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA high, then the master may abort the transmission by generating a STOP condition. When the master is receiving
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b7 - b0 b7 - b0 1-7 8 9 1-7 8 9 P DATA ACK DATA ACK STOP CONDITION
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data from the slave, the master pulls down the SDA line during the clock pulse to indicate receipt of the data. After the last byte has been received the master leaves the SDA line HIGH (not acknowledge) and issues a stop condition to terminate the transmission. Write Protocol The master begins communication with a START condition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 7. The addressed LTC4215 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. The LTC4215 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then delivers the data byte and the LTC4215 acknowledges once more and latches the data into its control register. The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte, as in a Write Word command, the second data byte is acknowledged by the LTC4215 but ignored, as shown in Figure 8. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 9. The addressed LTC4215 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to read. The LTC4215 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then sends a repeated START condition followed by the
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S 1 0 a4:a0
ADDRESS W A 00
FROM MASTER TO SLAVE FROM SLAVE TO MASTER
Figure 7. LTC4215 Serial Bus SDA Write Byte Protocol
S
ADDRESS W A 1 0 a4:a0 00
Figure 8. LTC4215 Serial Bus SDA Write Word Protocol
S
ADDRESS W A 1 0 a4:a0 00
Figure 9. LTC4215 Serial Bus SDA Read Byte Protocol
S
ADDRESS W A 1 0 a4:a0 00
COMMAND X X X X X b2:b0
Figure 10. LTC4215 Serial Bus SDA Read Word Protocol
ALERT S RESPONSE R A ADDRESS 0001100 1 0
Figure 11. LTC4215 Serial Bus SDA Alert Response Protocol
same seven bit address with the R/W bit now set to one. The LTC4215 acknowledges and send the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command, Figure 10, the LTC4215 repeats the requested register as the second data byte. Alert Response Protocol When any of the fault bits in FAULT register D are set, an optional bus alert is generated if the appropriate bit in the ALERT register B is also set. If an alert is enabled, the cor-
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COMMAND X X X X X b2:b0 A DATA A P 0 b7:b0 0 A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION
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COMMAND X X X X X b2:b0
A DATA A 0 b7:b0 0
DATA XXXXXXXX
AP 0
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COMMAND X X X X X b2:b0
AS 0
ADDRESS 1 0 a4:a0
R A DATA A P 1 0 b7:b0 1
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AS 0
ADDRESS 1 0 a4:a0
R A DATA A DATA A P 1 0 b7:b0 0 b7:b0 1
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DEVICE ADDRESS 1 0 a4:a0 0
AP 1
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responding fault causes the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4215 responds with its address on the SDA line and then release ALERT as shown in Figure 11. The ALERT line is also released if the device is addressed by the bus master. The ALERT signal is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated FAULT register bit has been cleared.
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DESCRIPTION Mass Write Alert Response 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DEVICE ADDRESS h BE 19 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E A0 A2 A4 A6 A8 AA AC AE B0 B2 B4 7 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
Table 1A. LTC4215 Device Addressing (UH24 Package)
DEVICE ADDRESS 4 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 3 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 2 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X LTC4215UH ADDRESS PINS ADR2 X X L L L L L L L L NC NC NC NC NC NC NC NC H H H H H H H H L NC H ADR1 X X NC H NC NC L H L L NC H NC NC L H L L NC H NC NC L H L L H H H ADR0 X X L NC NC H L H NC H L NC NC H L H NC H L NC NC H L H NC H L L L
Table 1B. LTC4215 Device Addressing (GN16 Package)
DESCRIPTION Mass Write Alert Response 0 1 2 DEVICE ADDRESS h BE 19 90 94 96 7 1 0 1 1 1 6 0 0 0 0 0 5 1 0 0 0 0 DEVICE ADDRESS 4 1 1 1 1 1 3 1 1 0 0 0 2 1 0 0 1 1 1 1 0 0 0 1 0 0 1 X X X LTC4215GN ADDRESS PINS ADR2 X X NC NC NC ADR1 X X NC NC NC ADR0 X X L NC H
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LTC4215 APPLICATIO S I FOR ATIO
Table 2. CONTROL Register A (00h)--Read/Write
BIT A7:6 NAME GPIO Configure OPERATION FUNCTION Power Good (Default) Power Good General Purpose Output General Purpose Input A5 A4 A3 A2 A1 A0 Test Mode Enable FET On Control Overcurrent Auto-Retry Undervoltage Auto-Retry Overvoltage Auto-Retry A6 0 0 1 1 A7 0 1 0 1 GPIO PIN GPIO = C3 GPIO = C3 GPIO = B6 C6 = GPIO
Enables Test Mode to Disable the ADC; 1 = ADC Disable, 0 = ADC Enable (Default) On Control Bit Latches the State of the ON Pin at the End of the Debounce Delay; 1 = FET On, 0 = FET Off Overcurrent Auto-Retry Bit; 1 = Auto-Retry After Overcurrent, 0 = Latch Off After Overcurrent (Default) Undervoltage Auto-Retry; 1 = Auto-Retry After Undervoltage (Default), 0 = Latch Off After Undervoltage Overvoltage Auto-Retry; 1 = Auto-Retry After Overvoltage (Default), 0 = Latch Off After Overvoltage
Mass Write Enable Allows Mass Write Addressing; 1 = Mass Write Enabled, 0 = Mass Write Disabled (Default)
Table 3. ALERT Register B (01h)--Read/Write
BIT B7 B6 B5 B4 B3 B2 B1 B0 NAME Reserved GPIO Output FET Short Alert EN State Change Alert Power Bad Alert Overcurrent Alert Undervoltage Alert Overvoltage Alert OPERATION Not Used Output Data Bit to GPIO Pin when Configured as Output. Defaults to 0 Enables Alert for FET Short Condition; 1 = Enable Alert, 0 = Disable Alert (Default) Enables Alert when EN Changes State; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert when Output Power is Bad; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Overcurrent Condition; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Undervoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Overvoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default)
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LTC4215 APPLICATIO S I FOR ATIO
Table 4. STATUS Register C (02h)--Read
BIT C7 C6 C5 C4 C3 C2 C1 C0 NAME FET On GPIO Input FET Short Present EN Power Bad Overcurrent Undervoltage Overvoltage OPERATION 1 = FET On, 0 = FET Off State of the GPIO Pin; 1 = GPIO High, 0 = GPIO Low Indicates Potential FET Short if Current Sense Voltage Exceeds 1mV While FET is Off; 1 = FET is Shorted, 0 = FET is Not Shorted Indicates if the LTC4215 is enabled when EN is low; 1 = EN Pin Low, 0 = EN Pin High Indicates Power is Bad when FB is low; 1 = FB Low, 0 = FB High Indicates Overcurrent Condition During Cool Down Cycle; 1 = Overcurrent, 0 = Not Overcurrent Indicates Input Undervoltage when UV is Low; 1 = UV Low, 0 = UV High Indicates VDD or OV Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low
Table 5. FAULT Register D (03h)--Read/Write
BIT D7:6 D5 D4 D3 D2 D1 D0 NAME Reserved FET Short Fault Occurred EN Changed State Power Bad Fault Occurred Overcurrent Fault Occurred Undervoltage Fault Occurred Overvoltage Fault Occurred Indicates Potential FET Short was Detected when Measured Current Sense Voltage Exceeded 1mV While FET was Off; 1 = FET is Shorted, 0 = FET is Good Indicates That the LTC4215 was Enabled or Disabled when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged Indicates Power was Bad when FB when Low; 1 = FB was Low, 0 = FB was High Indicates Overcurrent Fault Occurred; 1 = Overcurrent Fault Occurred, 0 = Not Overcurrent Faults Indicates Input Undervoltage Fault Occurred when UV went Low; 1 = UV was Low, 0 = UV was High Indicates Input Overvoltage Fault Occurred when OV went High; 1 = OV was High, 0 = OV was Low OPERATION
Table 6. SENSE Register E (04h)--Read/Write
BIT E7:0 NAME SENSE Voltage Measurement OPERATION Sense Voltage Data. 8-Bit Data with 151V LSB and 38.45mV Full Scale.
Table 7. SOURCE Register F (05h)--Read/Write
BIT F7:0 NAME SOURCE Voltage Measurement OPERATION Source Voltage Data. 8-Bit Data with 60.5mV LSB and 15.44V Full Scale.
Table 8. ADIN Register G (06h)--Read/Write*
BIT G7:0 NAME ADIN Voltage Measurement OPERATION ADIN Voltage Data. 8-Bit Data with 4.82mV LSB and 1.23V Full Scale.
*The ADIN pin is not available in the GN16 package.
U
4215fb
W
U
U
21
LTC4215 TYPICAL APPLICATIO S
VIN 12V R1 22.1k 1% R2 3.05k 1% UV VDD SDA SCL ALERT ON TIMER CTIMER 1mF RS 0.0015W Q1 Si7880DP R7 24.3k 1% R8 2.94k 1%
CF 0.1mF 15V
SDA SCL ALERT
GND BACKPLANE PLUG-IN CARD
VIN 5V SA14A 11.5k
0.1mF 1.74k 2.67k UV VDD SENSE+ SENSE- GATE SOURCE FB OV ON GPIO SDAI EN LTC4215UFD SDAO ADIN SCL ALERT SS INTVCC TIMER ADR0 ADR1 ADR2 GND NC 68nF 3.57k
Figure 13. 5A, 5V Backplane Resident Application with Insertion Activated Turn-On
22
U
+
R4 100k
R5 10W
R6 15k C1 22nF
CL 1000mF
SENSE- GATE LTC4215GN INTVCC ADR0 C3 0.1mF
SOURCE FB GPIO SS GND CSS 68nF
4215 F12
Figure 12. 12V, 12A Card Resident Application
0.005W
FDD3706
VOUT 12V 10.2k
10W
100k
LOAD
1mF
0.1mF
4215 F13
BACKPLANE PLUG-IN CARD
4215fb
LTC4215 PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 - .196* (4.801 - 4.978) .045 .005 .0532 - .0688 (1.35 - 1.75) .004 - .0098 (0.102 - 0.249) 16 15 14 13 12 11 10 9 .009 (0.229) REF
.007 - .0098 (0.178 - 0.249)
.254 MIN .150 - .165
0 - 8 TYP
.229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988)
.016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0204
1
23
4
56
7
8
UFD Package 24-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1696)
0.70 0.05 4.50 0.05 3.10 0.05 2.65 0.05 (2 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.65 0.05 (2 SIDES) 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 0.10 (2 SIDES) 0.75 0.05
2.65 0.10 (2 SIDES) R = 0.115 TYP 23 24
PIN 1 NOTCH R = 0.30 TYP
PIN 1 TOP MARK (NOTE 6)
0.40 0.05 1 2
5.00 0.10 (2 SIDES)
3.65 0.10 (2 SIDES)
(UFD24) QFN 0505
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
4215fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4215 TYPICAL APPLICATIO
GND INTVCC R10 3.3k 5V 2 -7V 8 R9 10k 6 CF 0.1F R1 22.1k 1% R2 1k 1% R3 2.05k 1% UV VDD OV SDAI SDAO SCL ON INTVCC INTVCC R12 10k -7V 2 8 6 R9 100k Q2 -7V BACKPLANE PLUG-IN CARD D1 5.6V -12V
4215 F14
3 HCPL-0300 5 SDA -12V INTVCC
6
8
5 HCPL-0300 3 R13 3.3k SCL
3 HCPL-0300 5
VIN -12V
Figure 14. 3A, -12V Card Resident Application with Optically Isolated I2C
RELATED PARTS
PART NUMBER LTC1421 LTC1422 LTC1642A LTC1645 LTC1647-1/LTC1647-2/ LTC1647-3 LTC4210 LTC4211 LTC4212 LTC4214 LTC4216 LT4220 LTC4221 LTC4230 DESCRIPTION Dual Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Dual Channel, Hot Swap Controller Dual Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Single Channel, Hot Swap Controller Negative Voltage, Hot Swap Controller Single Channel, Hot Swap Controller Positive and Negative Voltage, Dual Channel, Hot Swap Controller Dual Hot Swap Controller/Sequencer Triple Channel, Hot Swap Controller COMMENTS Operates from 3V to 12V, Supports -12V, SSOP-24 Operates from 2.7V to 12V, SO-8 Operates from 3V to 16.5V, Overvoltage Protection Up to 33V, SSOP-16 Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14 Operates from 2.7V to 16.5V, SO-8 or SSOP-16 Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10 Operates from -6V to -16V, MSOP-10 Operates from 0V to 6V, MSOP-10 or 12-Lead (4mm x 3mm) DFN Operates from 2.7V to 16.5V, SSOP-16 Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006
U
RS 0.0015 Q1 Si7880DP OUTPUT R5 10 R6 15k -12V SENSE+ SENSE- GATE SOURCE FB ADIN LTC4215UFD GPIO EN SS ADR0 ADR1 NC CTIMER 1F CSS 68nF ADR2 GND TIMER CL 1000F C1 22nF R7 24.3k 1% R8 2.94k 1% 2 C3 0.1F
4215fb LT 0307 REV B * PRINTED IN USA

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